Current microprocessor design verification environments rely on design verification engineers to triage and debug simulation failures. Triaging and debugging simulation failures are most often a tedious and time consuming task that requires a significant investment in human resources. The human resource investment is also typically the most expensive portion in verifying the design of a microprocessor. Moreover, to find a real design bug, design verification engineers may have to triage and debug thousands of simulation fails, which is time consuming and requires the engineers to manually process each simulation fail.
Conventional methods of categorizing simulation failures into known and unknown domains utilize either a manual approach or a scripts approach that are based on a human produced set of rules. The manual approach is time consuming and error prone. The scripting approach is usually constrained to a few simulation failing scenarios and requires an exact sequence of events leading up to the failure point to properly debug/categorize the failure. Oftentimes, the rules for both approaches are incorrectly written resulting in an overly broad grouping of failures and significantly slowing down the design verification process. Moreover, these approaches lack rules for identifying a potential simulation failure that results in an already categorized failing scenario signature but has a different root problem than the categorized failing scenario signature. The problems arising from the manual approach and the scripts approach can result in both design bugs making it into a developed microprocessor as well as introducing delays in the design bug discovery stage.